1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a large capacity dynamic random access memory device for decreasing an occupancy area by providing sense amplifier driving lines over sense amplifiers and memory cells.
2. Description of the Related Art
Recently, in a semiconductor memory device, it is required that an area of each portion in the semiconductor memory device be made small in accordance with increasing the capacity of a bit line. It is useful for decreasing the occupancy area of each portion in the semiconductor memory device to minutely form a configuration of the semiconductor memory device, and to provide efficient wirings.
Generally, in a semiconductor memory device, a plurality of lines are required, for example, bit lines, word lines, data buses, sense amplifier driving lines, column select lines, power supply lines, and the like. The bit lines are constituted by polycrystal silicon and a diffusion layer formed on a substrate, and the word lines are constituted by polycrystal silicon accompanied with a gate of the memory cell transistor, and a metal (aluminium) wiring backing the polycrystal silicon to decrease a resistance thereof. For example, the wiring layers are constituted by seven layers, i.e., four polycrystal silicon layers, two aluminium layers, and one diffusion layer. The sense amplifier driving lines and the data buses running in the lengthwise direction (word line direction) and the column select lines running in the lateral direction (bit line direction) are constituted in respective aluminium wiring over the memory portion. Nevertheless, the power supply lines for applying a low and a high voltage to each of the sense amplifier driving lines along the lengthwise direction are not formed over the memory portion but are formed in the circumference of the memory portion along the lateral direction, and data bus lines connected to the data buses and data latch circuit are formed in the circumference of the memory cell portion along the lateral direction. Namely, the areas for the power supply lines and the data bus lines along the lateral direction should be provided in the circumference of the memory cell portion. Furthermore, a plurality of sense amplifiers arranged as a line-shape in the lengthwise direction are connected to the same sense amplifier driving lines in the lengthwise direction, and thus a width of each sense amplifier driving line becomes large. Therefore, the occupancy area of the semiconductor memory device becomes large.
Furthermore, in the conventional semiconductor memory device, when the sense amplifier driving lines are running along the word line direction (sense amp line direction), all sense amplifiers in the sense amp line are driven by the same driving lines. Note, the width of the driving lines close to the power lines should be made large, as the currents flowing in all the sense amplifiers in the sense amp line are flown to the power lines through the driving lines close to the power lines.
Additionally, in recent years, the capacity of DRAM devices become large, and a memory cell of the DRAM is constituted by a solid structure of a three dimensional stacked capacitor cell. This stacked capacitor cell is useful for reducing an occupancy area of the memory cell without decreasing the capacitance thereof. In the circumference of the memory cell portion, a plurality of peripheral circuits, for example, a sense amplifier, a bit line driver, a row decoder, a column decoder, and the like, are provided. Note, these peripheral circuits are constituted by normal semiconductor elements whose height corresponds to a single layer, the memory cell is constituted by the three dimensional stacked capacitor cell whose height corresponds to a plurality of layers, and thus an excessive difference is caused at the border portion between the memory cell portion and the peripheral circuit portion. This level difference between the memory cell portion and the peripheral circuit portion can not be included in a depth of focus of a exposure system. Therefore, the aluminium wirings can not be freely formed over the memory cell portion and peripheral circuit portion in high accuracy, and thus an occupancy area of the DRAM device can not be decreased.